On/Off-Chip SI/PI Engineer
Core
Critical technical liaison providing hands-on SI/PI analysis to resolve HBM challenges and drive system-level co-optimization for advanced memory architectures.
Role type
Senior IC Signal/Power Integrity Engineer (HBM/DRAM)
Builds
Advanced HBM and next-generation DRAM architectures
Domain
Semiconductor memory (DRAM, HBM), high-speed signaling, electromagnetics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SI/PI analysis, on-/off-chip PDN analysis, high-speed channel analysis, 2.5D/3D IC architecture understanding, integrated modeling, 3D electromagnetic analysis, root cause analysis, system-level co-optimization
Preferred skills
AI-assisted analysis, automation, package/PCB layout review
Technologies
HFSS, SIwave, Sigrity, ADS, HSPICE, Allegro Design, APD
Responsibilities
Perform on-chip and off-chip SI/PI design and analysis for HBM and next-generation DRAM products; Verify system-level SI/PI robustness through integrated modeling and 3D electromagnetic analysis; Analyze root causes of SI/PI issues and establish improvement plans; Participate in technical engagements with key customers; Strengthen SI/PI capabilities for HBM and next-generation DRAM; Drive system-level co-optimization beyond standalone DRAM design
Seniority
Senior, hands-on IC
