Senior ASIC Physical Design Engineer
Core
Implement advanced SoCs for next-generation satellite and space systems, managing the full physical design flow from synthesis to GDSII.
Role type
Senior ASIC Physical Design Engineer
Builds
Mixed-signal SoCs for high-power satellites
Domain
Aerospace / Semiconductor Design
Required skills
ASIC physical design, timing closure, power optimization, physical verification, floorplanning, place & route, CTS, STA, DRC/LVS, IR drop, EM analysis, script automation, tapeout preparation
Preferred skills
null
Technologies
Synopsys ICC2, Fusion Compiler, Cadence Innovus
Responsibilities
Execute complete physical design flow for complex SoC blocks and top-level integration; Perform timing closure and optimization across multiple corners and modes; Collaborate with front-end, verification, and DFT teams; Work with external physical design service providers; Develop and maintain scripts and automation; Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis; Assist in chip-level integration, ECOs, and tapeout preparation; Contribute to methodology development and flow documentation.
Seniority
Senior, hands-on IC
