Principal ASIC Design Verification Engineer
Core
Verify functionality, performance, and robustness of custom silicon designs for high-power satellites.
Role type
Principal ASIC Design Verification Engineer
Builds
Custom silicon for high-power satellite platforms
Domain
Aerospace / Semiconductor Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, SystemVerilog Assertions (SVA), formal verification, constrained-random testing, root-cause analysis, coverage closure
Technologies
SystemVerilog, UVM, SVA
Responsibilities
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments; Build SystemVerilog/UVM test benches including agents, monitors, scoreboards, checkers, and coverage models; Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate; Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios; Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues; Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Seniority
Principal, hands-on IC
