Physical Design Engineer, Timing
Core
Converge multi-million-gate designs on advanced process nodes through static timing analysis (STA) and partner with cross-functional teams for final signoff and tapeout.
Role type
mid- to senior-level Physical Design Engineer (Timing)
Builds
high-performance AI semiconductor chips
Domain
Semiconductor / AI Hardware
Deliverable
production ML models | product features
Required skills
static timing analysis (STA), timing closure, SDC constraint writing, ECO development, clocking, CDC/RDC analysis, guardbanding, worst-case corner analysis, Python/Perl/Tcl scripting
Preferred skills
SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, AI-based automation
Responsibilities
Drive timing convergence across blocks, partitions, sections, and top-level designs; analyze timing violations and develop fixes; develop and validate bottom-up constraints; use scripting for automation and flow development
Seniority
Mid-level to Senior, hands-on IC
