FPGA Verification Engineer, Air Dominance and Strike
Core
Architect and implement UVM verification environments for flight-critical FPGA/SoC designs on AMD (Xilinx) platforms, ensuring compliance with DO-254 and safety standards.
Role type
Senior IC FPGA verification engineer (avionics)
Builds
Verification environments, test sequences, and regression suites for flight-critical avionics systems
Domain
Defense / Avionics / FPGA/SoC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, SVA, Object-oriented programming, Industry simulators (Questa, VCS, Xcelium, Vivado), Git workflows, Linux development
Preferred skills
Formal verification, CDC verification, Verification automation scripting (Python, Tcl), SoC and ARM-based embedded platforms, CI/CD integration
Technologies
AMD (Xilinx) FPGA/SoC, UVM, SystemVerilog, Questa, VCS, Xcelium, Vivado, Python, Tcl, Makefile, Nix
Responsibilities
Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards); Develop verification plans with traceability to system requirements; Author SystemVerilog Assertions (SVA) for protocol compliance; Build functional coverage models and drive code coverage analysis; Develop constrained-random and transaction-level test sequences; Debug failures using waveform tools and simulation logs; Collaborate with design engineers on RTL reviews and bug resolution; Support hardware validation and board bring-up; Author verification closure reports and coverage analysis summaries
Seniority
Mid-Senior, hands-on IC
