Physical Design Engineer, AI Accelerator IP
Core
End-to-end physical implementation of RISC-V CPU and AI accelerator IP blocks for external licensees, ensuring PPA targets and timing closure.
Role type
Senior IC physical design engineer (IP)
Builds
Hardened AI accelerator IP and RISC-V CPU blocks
Domain
Semiconductor / AI Hardware / RISC-V
Deliverable
production ML models
Required skills
Block-level physical design, PnR, timing closure, signoff (STA, LEC), floorplanning, power grid design, clocking strategies, low-power design (UPF, power gating, multi-Vt), scripting (Tcl, Python, Perl), industry tools (Innovus, ICC2/FusionCompiler, PrimeTime)
Preferred skills
Advanced node tapeout experience, multi-variant IP delivery, chiplet integration
Technologies
Innovus, ICC2, FusionCompiler, PrimeTime, UPF, LEF, DEF, GDSII
Responsibilities
Own physical implementation of IP blocks from synthesis to GDSII signoff, close critical paths and hit power budgets with RTL owners, deliver IP integration collateral (timing/power models, signoff reports), support multi-variant IP porting across nodes and foundries
Seniority
Senior, hands-on IC