Power Design Engineer
Core
Designing and integrating CPU chiplets into a System-in-package, focusing on power analysis, projections, and optimization across RTL, synthesis, and physical design stages.
Role type
Senior IC power design engineer (CPU chiplet)
Builds
High-performance RISC-V CPU chiplets for AI platforms
Domain
Semiconductor / ASIC design / AI hardware
Deliverable
production ML models
Required skills
Power analysis and optimization for complex ASICs, RTL/synthesis/physical design flow, Joules and PrimePower tools, Tcl scripting, Python or similar scripting
Preferred skills
UPF/CPF low-power intent, Verilog/SystemVerilog, CPU micro-architecture, thermal analysis
Technologies
Joules, PrimePower, Tcl, Python, SystemVerilog, RISC-V
Responsibilities
Define and maintain power vector plans for chiplet and chip-level coverage, drive power analysis on RTL and netlist to measure and optimize power, evaluate and propose new power optimization techniques, tabulate and compare power metrics across design iterations, correlate pre-silicon projections with post-silicon silicon measurements
Seniority
Senior, hands-on IC