Physical Design Engineer
Core
Developing cutting-edge multi-core in-memory compute SoCs for AI platforms.
Role type
Physical Design Engineer (ASIC)
Builds
Multi-core in-memory compute System-on-Chips (SoCs)
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
ASIC physical design flow (RTL to GDS), synthesis, floorplanning, place and route, timing analysis, physical verification, clock tree synthesis (CTS), IP integration (memories, I/Os, embedded processors), EDA tools (Fusion Compiler, Primetime, Calibre), scripting (Python, Tcl, Bash)
Preferred skills
device physics, spice simulation, analogue design, AI hardware or compute architecture
Technologies
Fusion Compiler, Innovus, Primetime, Calibre, Redhawk, Python, Tcl, Bash
Responsibilities
Support synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification tasks; Participate in constraint generation, timing analysis, and optimisation; Apply clock tree synthesis (CTS) techniques; Integrate IPs including memories, I/Os, and embedded processors; Write and maintain automation scripts in Python, Tcl, or Bash to support flow development; Debug physical design issues; Collaborate with architecture, RTL, and verification teams
Seniority
Mid-level (1-5 years experience)