Principal Physical Design Engineer
Core
Lead the full-chip physical design flow for complex SoC/silicon products in server, storage, and networking applications.
Role type
Principal Physical Design Engineer
Builds
Custom connectivity solutions and standards-based semiconductor products for hyperscalers and data center ecosystems
Domain
Semiconductor / Physical Design / AI Infrastructure
Deliverable
production ML models
Required skills
Synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification, Formal verification, System Verilog/Verilog, DFT, IP integration, Python/Perl scripting
Preferred skills
DFT test coverage and debug, ECO methodologies
Technologies
Cadence, Synopsys, 16nm/7nm nodes
Responsibilities
Drive full chip or block level ownership from architecture to GDSII, perform timing closure, execute physical verification, collaborate with IP vendors, develop and maintain backend design flows
Seniority
Principal, hands-on IC
