Principal Logic Design Engineer - UALink IP/Subsystem
Core
Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-performance interconnects and data movement.
Role type
Principal IC logic design engineer (interconnect/IP)
Builds
UALink IP/subsystems for rack-scale AI infrastructure
Domain
Semiconductor / High-performance interconnects / AI infrastructure
Deliverable
production ML models
Required skills
RTL and microarchitecture development, high-speed interconnects, coherent fabrics, computer architecture, networking concepts, SystemVerilog/Verilog, CDC, reset architecture, hardware design methodology
Preferred skills
UALink experience, PCIe/CXL/CCIX/CHI/Ethernet protocols, AI/accelerator systems
Technologies
SystemVerilog, Verilog, UALink, PCIe, CXL, CCIX, CHI, Ethernet
Responsibilities
Lead architecture and RTL development for UALink IP/subsystems, Translate protocol and system requirements into scalable hardware architecture, Design high-bandwidth, low-latency data paths and control logic, Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability, Define interfaces between UALink and other SoC/interconnect components, Drive design optimization for performance, power, area, and latency, Debug complex simulation and integration issues, Provide technical leadership and mentorship
Seniority
Principal, hands-on IC with mentorship
