Principal Logic Design Engineer
Core
Lead the development of complex IPs/subsystems for rack-scale AI connectivity solutions, covering architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.
Role type
Principal IC logic design engineer (connectivity IP)
Builds
Custom connectivity IPs and subsystems (PCIe, Ethernet, CXL, UALink, UCIe) for hyperscalers and ecosystem partners
Domain
Semiconductor hardware design, high-speed data interfaces, AI infrastructure
Required skills
RTL design (SystemVerilog/Verilog), micro-architecture, high-speed interface protocols (PCIe, Ethernet, CXL, UALink, UCIe), flow control, arbitration, error handling, timing closure, CDC, synthesis, post-silicon debugging
Preferred skills
Switching silicon experience, end-to-end cycle ownership (concept to silicon production)
Technologies
SystemVerilog, Verilog, PCIe, Ethernet, CXL, UALink, UCIe
Responsibilities
Translate system requirements into hardware architecture; design high-performance logic for controllers/subsystems; develop verification strategies with verification teams; collaborate with SoC integration and physical design teams; lead technical reviews and mentor senior engineers; support post-silicon debug and root-cause analysis
Seniority
Principal, hands-on IC with mentorship
