Silicon Digital IP / Subsystem Architect
Core
Define architecture and technical direction for complex semiconductor IPs and subsystems, owning the definition from requirements through implementation.
Role type
Senior IC Silicon Digital IP / Subsystem Architect
Builds
Custom connectivity solutions and standards-based semiconductor IP blocks for rack-scale AI infrastructure
Domain
Semiconductor, AI infrastructure, high-speed interconnects
Deliverable
production ML models | product features
Required skills
IP architecture, microarchitecture, ASIC/SoC design, digital design, computer architecture, memory systems, high-speed interfaces, coherent interconnects, performance modeling, system-level trade-offs
Preferred skills
PCIe, UALink, CXL, Ethernet, CCIX, CHI, AI/accelerator architectures, networking, compute, high-performance SoC, full IP lifecycle to silicon production
Technologies
PCIe, UALink, CXL, Ethernet, NVLink, AXI, APB, CHI, CCIX
Responsibilities
Define architecture for complex IP blocks and SoC subsystems; Translate system requirements into specifications and performance targets; Define microarchitecture, data/control paths, clocking, reset, power, and error handling; Evaluate architectural trade-offs; Define interfaces and protocols; Develop architecture specifications and technical documentation; Review RTL and verification strategies; Provide technical leadership and mentorship; Drive architecture reviews
Seniority
Senior, hands-on IC with mentorship responsibilities
