Tech Lead, Physical Design
Core
Lead physical design for complex SoC/silicon products in server, storage, and networking applications, driving designs from architecture to GDSII.
Role type
Senior IC physical design lead
Builds
Custom connectivity solutions and standards-based semiconductor products for hyperscalers and data center ecosystems
Domain
Semiconductor physical design, AI infrastructure, data center connectivity
Deliverable
production ML models | product features
Required skills
synthesis, place and route, CTS, extraction timing analysis/STA, physical verification, formal verification, System Verilog/Verilog, DFT, IP integration, Python/Perl scripting
Preferred skills
DFT test coverage and debug, ECO methodologies
Technologies
Cadence, Synopsys, 16nm/7nm processes
Responsibilities
Own full chip or block level designs from architecture to GDSII, execute timing closure and formal verification, collaborate with IP vendors for RTL and hard-mac blocks, utilize backend tools for physical design flows
Seniority
Senior, hands-on IC
