Principal Package Signal & Power Integrity
Core
Architecting, optimizing, and signing off package Signal Integrity (SI) and Power Integrity (PI) solutions for next-generation high-performance connectivity products.
Role type
Principal Package Signal & Power Integrity Engineer
Builds
High-performance IC packaging platforms including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect.
Domain
Semiconductor connectivity (PCIe, CXL, Ethernet, SerDes) and advanced packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (electrical architecture and validation)
Required skills
Package SIPI modeling and signoff, High-speed SerDes channel design (PCIe 5.0/6.0/7.0, PAM4), EM extraction and simulation, PDN design and analysis, Simulation-to-measurement correlation, Cross-functional technical leadership, Advanced packaging knowledge (chiplets, 2.5D/3D, silicon interposers)
Preferred skills
Silicon floor planning influence, Automation and scripting for SIPI flows, Allegro Package Designer (APD) usage, Optical package SIPI design (CPO/NPO)
Technologies
ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, VNA, TDR, High-speed oscilloscope
Responsibilities
Define package SIPI architecture and design strategy for high-performance connectivity products; Perform package and system-level SI and PI simulations to validate designs; Lead cross-functional execution across silicon, package design, PCB, and manufacturing teams; Drive simulation-to-measurement correlation strategy; Own SIPI simulation and signoff for advanced packaging platforms; Define substrate and interposer routing guidelines; Establish SIPI modeling standards and mentor engineers.
Seniority
Principal, hands-on IC technical leader
