Senior Design Verification Engineer
Core
Build and validate complex connectivity silicon for rack-scale AI infrastructure by developing scalable verification environments and integrating UVM and C/C++ workflows.
Role type
Senior Design Verification Engineer (Silicon/SoC)
Builds
High-bandwidth connectivity products connecting CPUs, GPUs, memory, storage, and networking devices
Domain
Semiconductor / AI Infrastructure / Connectivity Protocols
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, C/C++, DPI/PLI integration, constrained-random testing, verification planning, coverage analysis, Python/Perl automation, FPGA-based emulation, protocol validation (PCIe, Ethernet, NVMe, USB, DDR, InfiniBand)
Preferred skills
PCIe physical/link/transaction layer verification, DDR4/DDR5/HBM memory verification, SoC software debugging (kernels, drivers, U-Boot), third-party verification IP familiarity
Technologies
SystemVerilog, UVM, C/C++, Python, Perl, FPGA, PCIe, Ethernet, NVLink, NVMe, USB, DDR, InfiniBand
Responsibilities
Build and maintain UVM-based verification environments using SystemVerilog and C/C++ integration; Translate design specifications into verification plans, test strategies, and reusable test sequences; Create directed and constrained-random tests, transaction-level sequences, and user-controlled random constraints; Write assertions and cover properties, analyze coverage data, and drive closure against verification goals; Automate verification infrastructure and regression workflows using Python or Perl; Collaborate with RTL designers to isolate, debug, and resolve failures across simulation, co-simulation, and FPGA-based emulation; Apply third-party verification IP to validate protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe, and USB.
Seniority
Senior, hands-on IC
