Manager Design Verification
Core
Architect and deliver connectivity silicon for rack-scale AI clusters, owning RTL design execution from microarchitecture through synthesis sign-off.
Role type
Manager, Digital Design Engineer (Connectivity Silicon)
Builds
Custom connectivity solutions integrating PCIe, CXL, Ethernet, NVLink, and UALink for hyperscalers
Domain
Semiconductor / AI Infrastructure / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), synthesis flows, timing closure, CDC analysis, low-power design, high-speed serial interfaces (PCIe, Ethernet), SoC integration, design methodology, mentorship
Preferred skills
PCIe Gen5/Gen6, CXL, UALink, UCIe, Ethernet MAC/PCS, formal verification, emulation, assertion-based methodologies, advanced process nodes (7nm/5nm)
Technologies
Verilog, SystemVerilog, PCIe, CXL, Ethernet, NVLink, UALink, 7nm, 5nm
Responsibilities
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off; Drive design reviews, lint, CDC, and timing closure activities; Partner with architecture to translate specifications into implementation-ready microarchitecture; Collaborate with verification on testplans, coverage closure, and bug triage; Mentor junior engineers and contribute to design methodology, scripts, and best practices; Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
Seniority
Manager, hands-on IC
