Template Job
Core
Design and implement complex digital blocks for rack-scale AI connectivity silicon, ensuring silicon-ready quality from microarchitecture to tapeout.
Role type
Principal Software Integration Engineer (Digital RTL Design)
Builds
Custom connectivity silicon for hyperscaler AI clusters
Domain
Semiconductor / AI Infrastructure / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog, RTL design, synthesis flows, timing closure, CDC, low-power design, high-speed serial interfaces (PCIe, Ethernet), SoC integration
Preferred skills
PCIe Gen5/Gen6, CXL, UALink, UCIe, Ethernet MAC/PCS, formal verification, emulation, assertion-based methodologies, advanced process nodes (7nm/5nm)
Technologies
Verilog, SystemVerilog, PCIe, CXL, Ethernet, NVLink, UALink, COSMOS
Responsibilities
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off; Drive design reviews, lint, CDC, and timing closure activities; Partner with architecture to translate specifications into implementation-ready microarchitecture; Collaborate with verification on testplans, coverage closure, and bug triage; Mentor junior engineers and contribute to design methodology; Debug complex pre-silicon and post-silicon issues
Seniority
Principal, hands-on IC with technical leadership
