Hardware Design Engineering, Director - OEM, Silicon Validation Platforms & Rack-Scale Design - Taiwan
Core
Lead the establishment of Astera Labs' Taiwan hardware engineering center as the primary hub for OEM customer engagement, Silicon Validation Platform (SVB/EVB) design, and rack-scale product development in Asia.
Role type
Director of Hardware Design Engineering (Leadership)
Builds
Silicon Validation Boards (SVB/EVB), AI chassis, switch trays, CEM cards, and reference designs for connectivity ASICs.
Domain
Hardware engineering, high-speed connectivity, AI infrastructure, semiconductor validation.
Deliverable
production ML models | product features | physical/clinical work
Required skills
Hardware/PCB design, mechanical engineering, silicon bring-up, high-speed signal integrity, thermal design, team leadership, OEM relationship management, lab infrastructure setup.
Preferred skills
Experience with CXL, Ethernet, NVLink, PCIe, UALink technologies, hyperscale cloud architecture, cross-functional collaboration with Santa Clara HQ.
Technologies
CXL, Ethernet, NVLink, PCIe, UALink, retimers, re-drivers, connectivity ASICs, AI chassis, switch trays.
Responsibilities
Establish and lead the Taiwan engineering center; recruit and develop a multidisciplinary hardware team; design Silicon Validation Platforms and rack-scale products; provide expert design review and debug support for OEM customers; develop reference designs and hardware design guides; manage OEM relationships and joint development programs.
Seniority
Director, strategic leadership with hands-on technical engagement.
