Principal Engineer, SOC IP Systems & Lifecycle Management
Core
Architect and lead the development of an AI-powered IP Lifecycle Management and IP Quality Assurance platform to ensure SOC readiness, prevent late-stage integration breaks, and automate root-cause analysis for false pass scenarios.
Role type
Principal Engineer, AI-driven IP Lifecycle Management & Quality Assurance Platform
Builds
Scalable IPLM and IPQA tools for SOC QA and tape-out sign-out
Domain
Semiconductor IP Management, Physical Design, and AI-driven Automation
Deliverable
production ML models | product features
Required skills
IP & EDA tool mastery (PrimeTime, Calibre, Innovus, SpyGlass, etc.), Advanced Tcl/Python scripting, SystemVerilog, FinFET/GAA transistor properties, Liberty/LEF/DEF physical formats, DFT verification (scan-chain, MBIST), Power/Timing integrity (UPF, IR-drop, EM), Waiver management protocols
Preferred skills
Agentic AI workflow integration, Cross-view consistency auditing (RTL to GDSII), Heterogeneous integration standards
Technologies
PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate, Python, Tcl, SystemVerilog, FinFET, GAA, 5nm/3nm nodes
Responsibilities
Architect AI-driven automation for IP management and root-cause analysis; Verify IP compliance with high-speed interface standards; Perform independent LVS, DRC, and Antenna signoffs; Validate DFT requirements and fault coverage; Audit Power Domain consistency and Liberty timing models; Develop automated Waiver Audit Protocols; Track lessons learned and ensure release completeness
Seniority
Principal, hands-on IC with strategic platform leadership
