STA Physical Design Engineer, Senior Principal
Core
Senior Principal Physical Design Engineer driving planning, coordination, and execution for connectivity ASIC design from RTL to GDS for leading cloud service providers and OEMs.
Role type
Senior Principal IC Physical Design Engineer (Connectivity ASIC)
Builds
Connectivity ASICs (CXL, Ethernet, NVLink, PCIe, UALink) for hyperscalers and server/network OEMs
Domain
Semiconductor / Hardware Design / High-Speed Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL to GDS ownership, PnR, Timing closure, EM-IR, Formality, DRC/LVS, Synthesis, Place-and-route, SDC constraints, Hierarchical design management, ECO flow, Scripting (Tcl, Python, Perl), Cadence/Synopsys toolchains
Preferred skills
High-speed SERDES/Ethernet PHY timing, ECO methodologies, DFT tools, IP vendor integration, SystemVerilog/Verilog
Technologies
Cadence, Synopsys, PT DMSA, 7nm and below nodes
Responsibilities
Independently drive PnR activities from RTL to GDS ensuring robust signoff; Identify RTL issues early and collaborate with frontend teams; Manage I/O timing budgets across hierarchical designs; Partner with design, implementation, and verification teams for block/top convergence.
Seniority
Senior Principal, hands-on IC
