MTS - HIG HBM - ARCHITECTURE
Core
HBM IO Design Architecture Engineer focusing on IO/TSV design, electrical modeling, Signal Integrity (SI), and Power Integrity (PI) analysis for High Bandwidth Memory solutions.
Role type
Senior IC HBM IO Design Architecture Engineer
Builds
High-Performance Integrated Group (HIG) HBM solutions for AI and ML applications
Domain
Semiconductor / Memory and Storage / Advanced Packaging
Deliverable
production ML models
Required skills
High-speed IO design, Analog and digital design, Circuit verification, Layout verification, Parasitic extraction, Device characteristics, Advanced packaging knowledge (CoWoS, HBM stack, D2D), AI-assisted analytics, Simulation-to-silicon correlation
Preferred skills
Circuit debug experience, Product Engineering experience
Technologies
HBM, DDR, UCIe, PCIe, MIPI, PLL, Tx, Rx, Equalization, clock tree
Responsibilities
Define and standardize IO design quality process from architecture to silicon, Develop IO and TSV modeling methodologies, Drive simulation-to-silicon correlation and post-silicon learning feedback, Leverage AI Assisted analytics to accelerate root cause identification
Seniority
Senior, hands-on IC
