Principal Engineer - ASIC DV
Core
Lead ASIC Design Verification for IP/Block or Subsystem, ensuring first-pass product sign-off through comprehensive test plans and coverage.
Role type
Principal ASIC Design Verification Engineer (IP/Subsystem)
Builds
Verified IP blocks and subsystems for memory and storage solutions
Domain
Semiconductor / ASIC Design Verification
Required skills
System Verilog, UVM, AMBA protocols (AXI/AHB), PCIe/NVMe/DDR protocols, RTL debugging, Scoreboard, Assertions, Functional coverage, Code Coverage analysis
Preferred skills
NVMe controller experience, Security aspects (boot, ROM, FW protection), AI tools usage, Managing teams of 5+ DV engineers, Leading IP/Block to completion
Technologies
System Verilog, UVM, Verilog, AMBA, PCIe, NVMe, DDR
Responsibilities
Create test plans and develop System Verilog/UVM testbenches; Lead and mentor verification engineers; Ensure product sign-off via coverage criteria; Collaborate on core technical initiatives across locations
Seniority
Principal, hands-on IC with mentorship
