High-Speed Analog & Mixed-Signal PHY Design Engineer
Core
Design next-generation SerDes PHY blocks for SoCs in leading-edge CMOS nodes (7nm+), focusing on low-power analog and mixed-signal circuit designs.
Role type
Senior IC analog/mixed-signal design engineer (SerDes PHY)
Builds
High-speed, low-power SerDes PHY blocks for System-on-Chip (SoC) integration
Domain
Semiconductor / Analog Mixed-Signal / High-Speed Interface
Required skills
Analog/mixed-signal integrated circuit design, Transistor-level circuit design, Physical layout supervision, SerDes design, Clocking design, CADENCE, SPICE, MATLAB, Verilog/VHDL
Preferred skills
PhD in Electrical Engineering, VCO/PLL/DLL design, Audio CODEC/Class D Audio amplifier design, Delta-Sigma/SAR ADCs, Current-Steering DACs, high-speed DDR PHYs
Technologies
7nm CMOS, FinFET, CADENCE, SPICE, MATLAB, Verilog, VHDL
Responsibilities
Contribute to architecture and circuit designs for PHY blocks, Oversee block-level layout, Define and run simulations/analyses (power, performance), Debug design issues and escalate complex problems, Write detailed technical documentation
Seniority
Mid-level IC Engineer (2+ years experience)
