Next-Gen System Cache ASIC Digital Design Engineer
Core
Design, model, verify, and validate RTL for SOC Interconnects, Cache, and Memory Controllers for Snapdragon platforms.
Role type
Senior IC digital design engineer (cache/interconnect)
Builds
System-on-Chip (SoC) interconnects, cache controllers, and memory subsystems for smartphones, PCs, VR/AR, and automotive.
Domain
Semiconductor / SoC Design
Required skills
Verilog/SystemVerilog, Synopsys synthesis, low power design, coverage-based design verification, RTL design, micro-architecture, C/C++/Python
Preferred skills
Computer Architecture, Computer Arithmetic, CPU design, ASIC design experience, DV experience
Technologies
Verilog, SystemVerilog, Synopsys, C, C++, Python
Responsibilities
Micro-architect and design RTL for SOC Interconnects, Cache, and memory subsystems; Optimize hardware design for performance, power, and cost; Evaluate hardware feasibility of complex algorithms; Develop micro-architecture and specifications; Provide verification and debugging throughout project cycles; Troubleshoot silicon issues.
Seniority
Mid-level to Senior, hands-on IC
