DDRSS Systems Engineer
Core
Validate, tune, and optimize the DDR subsystem across pre-silicon and post-silicon platforms for Qualcomm products.
Role type
Senior IC embedded systems engineer (memory subsystem)
Builds
Low-level firmware and system APIs for DDR subsystem initialization, training, power management, and performance features
Domain
Semiconductors / Mobile SoC / Memory Subsystems
Required skills
C programming, embedded firmware development, system debugging, hardware/software integration, digital design fundamentals, computer architecture, LPDDR protocol knowledge, lab equipment usage, silicon debugging tools
Preferred skills
LPDDR4/5/5X protocol expertise, training algorithms, timing parameters, post-silicon bring-up, Verilog/SystemVerilog simulation, memory controllers, caches, coherent interconnects, SoC architecture, performance analysis, power optimization, emulation platforms, FPGA prototyping, Python scripting
Technologies
C, Verilog, SystemVerilog, Python, LPDDR, FPGA, Emulation platforms
Responsibilities
Develop and maintain low-level firmware and system APIs for DDR subsystem initialization, training, power management, and performance features. Validate firmware functionality in simulation, emulation, FPGA, and silicon environments. Analyze and debug system issues spanning hardware, firmware, and software domains. Collect and interpret stability, performance, power, and reliability data to guide design and product decisions. Collaborate across design, DV, software, architecture, and product teams to enable and optimize DDR features. Perform DDR subsystem bring-up and characterization on pre-silicon and post-silicon platforms. Debug memory subsystem issues involving LPDDR interfaces, caches, interconnects, and memory controllers.
Seniority
Mid-level, hands-on IC
