Staff Verification Engineer, Compute Subsystems
Core
Develop world-class ML HW solutions and multimedia/compute subsystem integration verification strategies for ASICs.
Role type
Staff IC ASIC design verification engineer
Builds
Multimedia and compute subsystems for ML hardware
Domain
Semiconductors / ASIC Design / Machine Learning Hardware
Deliverable
production ML models
Required skills
UVM, System Verilog, Digital design concepts, Bus protocols (AHB/AXI), Perl/Python scripting, C programming, RTL code coverage, Assertion coverage, Functional coverage, Gate level simulations, Power aware verification
Preferred skills
New verification methodologies, Productivity improvements
Technologies
UVM, System Verilog, C, Perl, Python
Responsibilities
Develop multimedia and compute subsystem integration verification strategy and test plan; Create verification environment using UVM/System Verilog; Resolve architecture, design, or verification problems; Write tests and regressions; Develop C reference model; Interpret performance check results; Perform RTL code coverage, assertion coverage, functional coverage, and gate level simulations; Employ power aware verification techniques.
Seniority
Staff, hands-on IC
