Physical Design Sr / Lead / Staff Engineer - Camera
Core
Senior Physical Design Engineer responsible for end-to-end implementation of Camera SoC designs, optimizing Power, Performance, and Area (PPA) from netlist to GDSII.
Role type
Senior IC Physical Design Engineer (Camera SoC)
Builds
High-performance Camera System-on-Chip (SoC) designs
Domain
Semiconductor / VLSI / Hardware Engineering
Required skills
Floorplanning, Place & Route (PNR), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Low-power design, IR drop analysis, Physical verification, Scripting (Perl, Python, TCL), ECO implementation
Preferred skills
Deep submicron technology nodes, High-performance implementation techniques
Technologies
Fusion Compiler (FC), Genus, Innovus, PrimeTime (PT), Tempus, Voltus, RedHawk, Tweaker
Responsibilities
Collaborate with cross-functional teams to address critical physical design challenges in Camera PNR implementation, Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets, Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues, Partner with block-level implementation teams to analyze and improve optimization methods
Seniority
Senior, hands-on IC
