Formal Verification CAD Engineer
Core
Drive formal verification of complex hardware design blocks using advanced formal tools and convergence strategies to achieve high-confidence sign-off.
Role type
Senior IC formal verification engineer (hardware)
Builds
Hardware design blocks for mobile processors and systems
Domain
Semiconductor hardware design and verification
Required skills
Formal verification fundamentals, proof strategies, abstraction techniques, formal tools (Jasper, VC Formal, Questa Formal), Python scripting, analytical problem-solving
Preferred skills
Property-based formal verification (SVA), low-power verification methodologies (UPF/CPF, power/clock gating)
Technologies
Jasper, VC Formal, Questa Formal, Python, UPF, CPF
Responsibilities
Drive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies. Review and refine formal setups, proofs, constraints, and abstractions with design/DV teams. Develop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows. Analyze challenging formal problems and propose effective verification strategies. Engage with EDA vendors to evaluate advanced DV methodologies.
Seniority
Mid-level, hands-on IC
