SOC Power/Limits Architect
Core
Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health against physical, electrical, and thermal constraints.
Role type
Senior IC SoC Power/Limits Architect
Builds
Next-generation SoC systems balancing high performance with power/thermal constraints
Domain
Semiconductor / ASIC Design / Power Management
Required skills
ASIC design, power management, low-power design methodologies, C/C++, Python, architectural modeling, firmware prototyping, post-silicon validation, telemetry design
Preferred skills
Sensing IP development, voltage/current/temperature sensing, performance profiling, workflow automation
Technologies
C, C++, Python
Responsibilities
Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations; Lead cross-functional teams to standardize mitigation features (Power Telemetry, Estimators, Droop Detectors); Drive evolution of Sensing IPs (Voltage, Current, Temperature); Design real-time telemetry requirements; Drive organizational consensus on feature ROI; Oversee Post-Silicon Validation; Correlate post-silicon power with pre-silicon models.
