Analog / Mixed-Signal IP DDR Design Senior Engineer - Cork, Ireland
Core
Design high-speed analog/mixed-signal IP blocks (Rx/Tx IO, DLL, clocking) for DDR and Chip-to-Chip PHYs in leading-edge FinFET/GAA nodes.
Role type
Senior IC analog/mixed-signal engineer (DDR PHY)
Builds
Production analog/mixed-signal IP blocks for Snapdragon SoC products
Domain
Semiconductors, High-speed analog/mixed-signal design
Required skills
Transistor-level analog/mixed-signal design, SPICE simulation, Schematic capture, Op-amp design, Bandgap design, PLL/DLL design, High-speed DDR/SerDes design, Signal integrity analysis, Full-custom layout, Pre-silicon validation
Preferred skills
GenAI for design automation, Signal integrity expertise
Technologies
SPICE, Schematic capture tools, FinFET, GAA
Responsibilities
Architecture and design of high-speed mixed-signal circuits for LPDDR5/6, Custom block design (Rx/Tx, clocking, references), Circuit design for chip-to-chip architectures, Schematic capture and SPICE analysis, Post-silicon bringup support, Collaboration with Physical Design teams, Power and Signal integrity analysis
Seniority
Senior, hands-on IC
