STA Staff Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products.
Role type
Staff Engineer, Static Timing Analysis (STA) & Physical Implementation
Builds
ASIC blocks and SoCs for next-generation communication and data processing products
Domain
Semiconductor / ASIC Design / Digital & Analog
Required skills
Static Timing Analysis (STA), Physical Implementation, Timing Constraints, ECO Generation, Perl scripting, TCL scripting, Deep submicron process technology, Power minimization, PPA optimization
Preferred skills
High performance and low power implementation methods, Extreme critical timing bottleneck resolution, Complex ECOs across huge set of corners
Technologies
PT, Tempus, GENUS, Innovus, ICC
Responsibilities
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development; Solve extreme critical timing bottleneck paths; Prepare complex ECOs for timing convergence; Minimize power consumption; Push PPA to the best possible extent.
Seniority
Staff, hands-on IC
