Staff Engineer- Power Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products.
Role type
Staff ASIC Power Engineer
Builds
Digital and/or analog IP blocks and SoCs for next-generation communication and data processing products
Domain
Semiconductor / ASIC Design / Low Power Optimization
Deliverable
production ML models
Required skills
RTL power optimization, PowerArtist/PTPX/PowerPro, low-power design techniques (clock gating, power gating), emulation power flow, backend flows (logic synthesis, place-and-route), Python programming for automation and AI/ML-driven analysis, debugging RTL/gate-level power anomalies
Technologies
PowerArtist, PTPX, PowerPro
Responsibilities
Collaborate with cross-functional groups to determine product execution path; debug RTL or gate-level power anomalies and identify root-cause structures; build automation scripts and data pipelines for RTL power optimization
Seniority
Staff, hands-on IC
