High Performance DSP core Implementation(Synthesis) Staff Engineer
Core
Staff Engineer responsible for Physical Synthesis, timing closure, and low-power implementation of high-performance ASICs and SoCs.
Role type
Staff IC ASIC Synthesis Engineer
Builds
High-performance, low-power digital and analog IP blocks and SoCs
Domain
Semiconductor / VLSI Design
Required skills
Physical Synthesis, Timing Closure, Multi-clock domain design, MCMM optimization, Low-power design (UPF), Scripting (Python/Tcl/Perl), Equivalence Checking, ECO handling, Formal Verification
Preferred skills
Version Control, Configuration Management, Regression testing
Technologies
Fusion Compiler, Genus, LEC, LP signoff tools, Verilog, VHDL, UPF
Responsibilities
Write timing constraints for synthesis and STA; Perform timing closure for multi-clock domain designs; Optimize designs using MCMM and low-power techniques; Handle ECOs and formal verification; Collaborate with design, DFT, and PD teams for netlist delivery.
