CPU STA Engineer, Sr Engineer
Core
Senior CPU Static Timing Analysis (STA) Engineer responsible for timing closure, constraint management, and verification of high-speed CPU micro-architectures within ASIC flows.
Role type
Senior IC hardware engineer (CPU STA)
Builds
High-speed CPU ASICs with optimized timing, power, and performance
Domain
Semiconductor hardware design (CPU micro-architecture)
Required skills
Static Timing Analysis (STA), Place & Route (Innovus/FC), ASIC flow optimization, UPF/CPF power domain implementation, Clock Tree Synthesis, Constraint generation and validation, Formal verification, Perl/Tcl/Python/C++ scripting, Verilog coding
Preferred skills
Low power implementation techniques, High speed CPU implementation experience
Technologies
Innovus, FC, Primetime, Tempus, Formality, Conformal, UPF, CPF, Verilog
Responsibilities
Perform static timing analysis and closure for CPU designs; Generate and validate timing constraints; Implement clock trees for high-speed designs; Execute formal verification; Script automation using Perl/Tcl/Python/C++
Seniority
Senior, hands-on IC
