CPU Server FV/CLP/STA engineer
Core
Design, optimize, verify, and test CPU electronic systems including synthesis, timing analysis, and power checks for cutting-edge products.
Role type
Senior IC CPU Server FV/CLP/STA engineer
Builds
CPU designs and electronic systems
Domain
Semiconductor / CPU Design
Required skills
Multi-million gate synthesis, Physical synthesis (DC, Genus, Fusion Compiler), Multi-clock domain timing analysis, Multi-power domain synthesis (CLP), Formal verification, Pre-layout STA, Timing ECO generation, Timing/area/power/congestion trade-offs, TCL scripting
Preferred skills
Hierarchical STA with Hyperscale
Technologies
DC, Genus, Fusion Compiler, CLP, TCL
Responsibilities
Handle complex data path oriented Multi-million gate synthesis; Develop constraints for multi-clock domains hierarchical/flat timing analysis; Perform multi-power domain synthesis and structural power checks using CLP; Conduct Formal verification and debug issues/aborts; Analyze timing reports and generate timing ECOs; Analyze trade-offs and recipes for timing/area/power/congestion; Write TCL scripts for Synthesis/STA usage.
