Front-End Implementation Engineer (Staff) (Timing & Synthesis)- Cork, Ireland
Core
Creating top-level timing constraints, physical synthesis, formal verification, and functional ECOs to bridge RTL and physical design for Snapdragon SoCs.
Role type
Staff Front-End Implementation Engineer (ASIC)
Builds
Snapdragon SoCs at the core and chip-level in 4nm and below technology
Domain
Semiconductor / ASIC Design
Required skills
Logical/Physical synthesis, DFT implementation, timing closure in STA, timing constraint capture in TCL, formal verification, Verilog RTL design, UPF, Low power checks, Static Timing Analysis, TCL/PERL/Python script development
Preferred skills
Design for test concepts, large complex SoC devices timing constraint development
Technologies
Synopsys tools, Verilog, TCL, PERL, Python, UPF
Responsibilities
Drive and execute all phases of the design flow for Snapdragon SoCs, create top-level timing constraints, perform physical synthesis, conduct formal verification, implement functional ECOs, develop TCL scripts for Synopsys tools, perform low power checks and Static Timing Analysis.
Seniority
Staff, hands-on IC
