RTL Design (SOC) Engineer-Staff
Core
Design and development of high-speed serial IO protocols, clock rate compensation FIFO, gearbox design, power gating, and low power modes for Qualcomm's Dragonfly rack-scale Agentic AI platform.
Role type
Staff RTL Design Engineer (SoC)
Builds
Next-gen architectures for Qualcomm's Dragonfly Agentic AI platform
Domain
Semiconductor / Hardware Engineering / Data Center AI
Deliverable
production ML models
Required skills
SoC development, full-chip design, design convergence cycle (architecture, micro-architecture, verification, synthesis, timing closure), IP dependency management, high-speed serial IO protocols, bus protocols (AHB, AXI, PCIe, USB, Ethernet), memory controller design
Preferred skills
Microprocessor design, test plan review, coverage metrics analysis
Technologies
AHB, AXI, PCIe, USB, Ethernet
Responsibilities
Plan front-end design tasks, manage IP dependencies, implement clock rate compensation and power gating strategies, design high-speed serial IO protocols
Seniority
Staff, hands-on IC
