Digital Design R&D Engineer (Lead/Staff)
Core
Lead digital design R&D engineer optimizing performance, power, and area (PPA) for performance cores (GPU, AI, Modem, DDR) using ML solutions for timing closure.
Role type
Staff/Lead Digital Design R&D Engineer (VLSI/SoC)
Builds
High-performance SoCs and digital cores for next-generation connected devices
Domain
Semiconductor / Hardware Engineering / Digital VLSI
Deliverable
production ML models
Required skills
Digital VLSI implementation (netlist to GDS), PNR implementation, STA, EDA tools (Primetime, FC, Innovus, Tempus), Python, TCL, ML algorithms
Preferred skills
Big-Data/ML/Analytics for design convergence
Technologies
Python, TCL, Primetime, FC, Innovus, Tempus
Responsibilities
Improve PPA for performance cores like GPU, AI, Modem and DDR; Develop ML solutions for faster and smarter timing closure for the SoC; Use Big-Data/ML/Analytics in digital design to guide better design choices and improve convergence times
Seniority
Staff/Lead, hands-on IC
