Senior HSIO/DDR Bench Test Engineer
Core
Develop test methodologies and characterize High Speed SERDES Interfaces (PCIe, USB3, UFS, DP, MIPI) and LP-DDR/PC-DDR subsystems for highly integrated SOCs.
Role type
Senior IC test engineer (High Speed Interfaces & DDR)
Builds
Test solutions and characterization plans for System on Chip (SoC) designs
Domain
Semiconductor / Hardware Engineering
Required skills
High Speed SERDES characterization, DDR protocol knowledge, Signal Integrity (SI) analysis, Power Integrity (PI) analysis, Mixed-signal circuit physics, VLSI technologies, Lab equipment operation (Oscilloscopes, TDRs/VNAs, J-BERT), Python/C# for test automation
Preferred skills
Eye diagram analysis, Jitter analysis, Transmitter/Receiver design blocks, Board design concepts, ASIC device level characterization, System level knowledge
Technologies
PCIe, USB3, UFS, DP, MIPI (DSI, CSI), LP-DDR, PC-DDR, Mixed Signal PHY IP, Python, C#
Responsibilities
Define and execute test methodologies for High Speed Interfaces, Develop and execute characterization plans to optimize design parameters, Drive first silicon bring up and debug for external foundries, Assist in HW design and debug power integrity (PI) and signal integrity (SI) issues, Perform technical data analysis of parametric performance, Resolve customer issues/RMA debug
Seniority
Senior, hands-on IC
