SOC Design Implementation Engineer
Core
Design and implement RTL synthesis, DFT insertions, timing constraints, and static timing analysis flows for digital/analog/RF/optical systems to achieve performance, power, and area optimization.
Role type
Senior IC hardware design implementation engineer (RTL/DFT/STA)
Builds
Digital/Analog/RF/optical systems, equipment, and packaging for cutting-edge consumer and infrastructure products
Domain
Semiconductor hardware engineering (RTL, DFT, STA, FPGA, DSP)
Required skills
RTL synthesis, DFT insertions (MBIST, SCAN), timing constraint setup, static timing analysis (STA), ECO flows, logic equivalency checks, gate-level netlist analysis, constraints debugging
Preferred skills
FPGA/DSP system experience, cross-functional collaboration, yield optimization
Technologies
STA tools, DFT tools, RTL synthesis tools, gate-level netlists
Responsibilities
Perform RTL synthesis to optimize Performance/Power/Area; Execute DFT insertions including MBIST and SCAN; Setup timing constraints for functional and test modes; Run static low-power checks on gate level netlists; Verify logic equivalency between RTL-to-Gates and Gates-to-Gates; Manage signoff Static Timing Analysis and ECO flows to achieve timing closure; Perform timing analysis and constraints debugging
