Senior Leader, Signal and Power Integrity/Systems Architecture (High-Speed Interconnects) - Multiple locations
Core
Define, develop, and productize next-generation high-speed electrical interconnect technologies for AI, hyperscale datacenter, networking, and HPC platforms.
Role type
Senior Leader, Electrical Systems Architect (High-Speed Interconnects)
Builds
End-to-end architecture for 224G and 448G PAM4 electrical interconnect systems, including SerDes, package, PCB, connector, cable, CPC, NPC, flyover, and rack-scale connectivity solutions.
Domain
Semiconductor/Telecommunications (High-Speed Interconnects, AI Infrastructure)
Required skills
224G/448G PAM4 signaling, SerDes architectures, Signal Integrity (SI), Power Integrity (PI), advanced packaging, PCB design, connector technologies, end-to-end electrical system analysis, channel budgeting, COM analysis, PDN design, simulation-to-silicon correlation, PHY/SerDes architectures, equalization techniques, FEC, system performance tradeoffs
Preferred skills
224G+ and 448G electrical interconnect solutions, CPC/NPC copper flyover architectures, AECs, advanced package substrates, next-generation PCB technologies, Ethernet/PCIe/UALink/NVLink/OIF CEI/IEEE 802.3, chiplets, UCIe, heterogeneous integration, EIC/PIC interfaces
Technologies
ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, PowerSI, Clarity, SystemVerilog, Verilog-A, COM analysis tools, IBIS-AMI modeling
Responsibilities
Define and drive end-to-end architecture for next-generation 224G and 448G PAM4 electrical interconnect systems; Lead system-level Signal Integrity (SI) and Power Integrity (PI) strategy; Drive architecture, modeling, and optimization of high-speed link technologies; Partner across silicon, package, board, power, and system teams to develop and productize advanced electrical connectivity solutions; Provide technical leadership for future interconnect roadmaps
Seniority
Senior, hands-on IC with leadership responsibilities
