Design Verification Engineer — Memory Subsystem (Vancouver)
Core
Develop and execute comprehensive verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM, PHY-related logic, and high-performance memory subsystem components.
Role type
Senior IC design verification engineer (memory subsystem)
Builds
Reusable SystemVerilog/UVM verification environments, testbenches, assertions, and coverage models for ASIC/SoC memory interfaces
Domain
Semiconductor / ASIC Design / Memory Subsystems
Required skills
SystemVerilog, UVM, SystemVerilog Assertions, constrained-random verification, coverage-driven verification, waveform analysis, regression execution, digital design fundamentals, clocking/reset behavior, multi-clock-domain designs
Preferred skills
LPDDR/DDR/HBM verification, JEDEC specifications, memory controller/PHY architecture, formal verification, power-aware simulation (UPF), AXI/APB/DFI protocols, hardware/software co-verification
Technologies
SystemVerilog, UVM, Verilog, waveform viewers, simulation logs, transaction databases
Responsibilities
Develop verification strategies, test plans, and coverage plans; Build and maintain UVM components (sequences, drivers, monitors, scoreboards, agents); Create constrained-random and corner-case tests; Write and maintain SystemVerilog Assertions; Analyze simulation failures and perform root-cause analysis; Collaborate with RTL, architecture, and integration teams; Drive functional, code, assertion, and coverage closure
Seniority
Senior, hands-on IC
