Clocking Systems Engineer, Staff
Core
Developing industry-leading DSP and mixed-signal SerDes architectures and solutions, with a focus on clock generation, clock recovery, and timing synchronization.
Role type
Staff IC systems engineer (clocking/SerDes)
Builds
High-speed communication products (SerDes, PLLs, CDRs, Retimers)
Domain
Semiconductors / High-speed digital communications
Deliverable
production ML models | product features
Required skills
DSP and mixed-signal PLL design, Clock and Data Recovery (CDR) architectures, Jitter and phase noise analysis, Behavioral/system-level modeling (MATLAB, Python, SystemVerilog), Simulation and verification automation, Model-to-silicon correlation
Preferred skills
112G/224G+ SerDes experience, Analog/mixed-signal PLL building blocks (phase detectors, interpolators, DCOs), RTL development, Silicon validation
Technologies
MATLAB, Python, SystemVerilog
Responsibilities
Develop behavioral and system-level models for PLLs, CDRs, Retimers, and clock distribution networks; Analyze system performance and architectural tradeoffs; Support silicon bring-up and investigate clocking-related performance issues; Improve simulation efficiency through automation and regression frameworks; Collaborate with analog, digital, firmware, and validation teams; Document technical analyses and validation results.