RTL Design Engineer, Sr Lead
Core
Develop detailed micro-architecture specifications and implement synthesizable RTL for front-end ASIC/SoC design, ensuring quality through lint, CDC, and timing analysis.
Role type
Senior IC RTL Design Engineer (ASIC/SoC)
Builds
Front-end ASIC/SoC blocks and subsystems
Domain
Semiconductor hardware design
Required skills
Verilog/SystemVerilog, Micro-architecture definition, Lint analysis (SpyGlass/Questa), CDC/RDC analysis, Digital design fundamentals, Clocking architectures, Reset strategies, Low-power design concepts, RTL debugging
Preferred skills
Synthesis flows (Design Compiler/Genus), Timing constraints (SDC), Timing analysis (setup/hold, CDC closure), DFT methodologies, Low-power techniques (UPF/CPF), Complex SoC/IP integration
Technologies
Verilog, SystemVerilog, SpyGlass, Questa Lint, SpyGlass CDC, Questa CDC, Design Compiler, Genus, SDC, UPF, CPF
Responsibilities
Develop detailed micro-architecture specifications from high-level requirements; Design and implement synthesizable RTL; Perform lint analysis and cleanup; Conduct CDC/RDC analysis and closure; Develop and maintain design documentation; Collaborate with verification teams to define plans and resolve issues; Support synthesis, timing analysis, and closure activities; Analyze and debug issues across simulation and implementation stages.
Seniority
Senior, hands-on IC
