Synthesis Engineer, Sr Lead
Core
Senior Physical Synthesis Engineer responsible for timing closure, optimization, and netlist delivery for hardware designs.
Role type
Senior IC physical synthesis engineer
Builds
Hardware netlists and timing-optimized designs for semiconductor chips
Domain
Semiconductor hardware design
Required skills
Physical synthesis, timing closure, multi-clock domain design, MCMM, low-power design (UPF), scripting (Perl/Python/TCL), ECOs, formal verification
Technologies
Synopsys Design Compiler, Cadence Genus, UPF, Perl, Python, TCL
Responsibilities
Write timing constraints for synthesis and STA, perform timing closure and pipelining, handle ECOs and formal verification, collaborate with design/DFT/PD teams, optimize power using clock gating
Seniority
Senior, hands-on IC
