ASIC Design Verification Engineer (Santa Clara, CA)
Core
Develop comprehensive pre-silicon test planning, testbenches, and verification methodologies for digital power IP within complex SoC systems.
Role type
ASIC Design Verification Engineer
Builds
Digital power IP and SoC subsystems
Domain
Semiconductor / SoC Design
Required skills
SystemVerilog, UVM, Assertion-based verification, C++, Python, Formal verification, Coverage development, Memory verification VIPs
Preferred skills
DDR protocol verification, Cache verification, Power/performance verification, PASIM simulations, Firmware/driver development
Technologies
UVM, SystemVerilog, C++, Python, DDR, Cache, SoC
Responsibilities
Develop testbenches using SystemVerilog-UVM for digital power IP, Create assertion models and coverage plans, Perform formal verification (property checking), Develop automation to improve verification efficiency, Verify complex SoC subsystems including caches and DDR memory protocols.
Seniority
Mid-level, hands-on IC
