Staff Engineer, Physical Design/Implementation
Core
Lead end-to-end physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes.
Role type
Staff IC Physical Design Engineer (ASIC)
Builds
High-performance silicon chips (retimers, SoCs) for communication and data processing
Domain
Semiconductor / ASIC Physical Design
Required skills
End-to-end ASIC Physical Design flow, Timing closure and signoff, Physical verification (DRC/LVS/DFM/DFY), EDA tools (Cadence Innovus, Synopsys ICC2), Power delivery and reliability (IR/EM), Clocking architectures and CTS, Large-scale SoC integration
Preferred skills
High-speed SerDes / retimer designs, Full-reticle or near-reticle SoC implementation, Multi-die / chiplet / advanced packaging, Data center/networking/optical connectivity ASICs, Scripting and automation (Python, Tcl)
Technologies
Cadence Innovus, Synopsys ICC2, Python, Tcl
Responsibilities
Lead and execute end-to-end Physical Design flow (Floorplanning, CTS, Placement & Routing, PDN, Timing analysis), Plan and implement full-chip or hierarchical designs, Drive timing closure across all corners and modes, Perform and review physical verification checks, Collaborate with cross-functional engineering teams, Lead integration of high-speed SerDes macros and mixed-signal IP, Drive IR/EM closure, power optimization, and congestion mitigation, Provide schedules, risk assessment, and execution tracking, Act as a strong technical contributor in design reviews and project meetings, Develop and improve physical design methodologies and flows
Seniority
Staff, technical leadership & execution
