CPU PDN & EM/IR Sign-Off Engineer (Lead/Staff)
Core
Lead/Staff engineer responsible for CPU Power Distribution Network (PDN) and Electromagnetic/IR sign-off for high-performance cores and chip top-level blocks.
Role type
Senior IC Power Integrity Engineer (CPU PDN & EM/IR)
Builds
High-performance CPU/DSP SoCs and packaging solutions
Domain
Semiconductor hardware design, Power Integrity, Packaging
Required skills
PDN sign-off, Power Integrity sign-off checks, PG Grid specification, Grid Resistance checks, Static/Dynamic IR drop validation, IO/Bump planning, RDL routing strategy, EDA tool scripting (Python, Perl, TCL), Cross-functional collaboration
Preferred skills
Redhawk/RHSC/Voltus expertise, Innovus for RDL/Bump Planning, Power Planning/Floorplanning, LSF/compute optimization
Technologies
Redhawk, Redhawk_SC, Voltus, Innovus, Fusion Compiler, Python, Perl, TCL
Responsibilities
Perform IR sign-off for CPU/high-performance cores; Execute Signal EM and Power EM sign-off for chip top-level and block-level CPU/DSP; Develop PG Grid specifications; Validate PG Grid using Grid Resistance and Secondary PG Resistance checks; Validate IR drops using Static IR, Dynamic IR Vless, and VCD checks; Plan IO, Bumps, and RDL routing strategies; Partner with SOC and Packaging teams on Bumps Assignments, RDL Enablement, and Pkg Routing Optimizations; Partner with EDA tool vendors and internal CAD teams to develop automation flows.
Seniority
Staff/Lead, hands-on IC
