CPU STA/Timing Engineer (Lead/Staff/Sr Staff)
Core
Drive timing analysis and closure for complex, multi-GHz CPU core and uncore designs across block, cluster, and full-chip hierarchies to meet aggressive frequency and power targets.
Role type
Senior IC CPU Physical Design Timing (STA) Engineer
Builds
High-performance CPU cores and uncores for Qualcomm SoCs
Domain
Semiconductor / CPU Physical Design
Required skills
Static Timing Analysis (STA), timing closure, multi-clock/multi-domain design, deep sub-micron technology nodes, timing ECOs, standard cell libraries, HDL (Verilog), synthesis/place & route flows, noise/cross-talk analysis, OCV/variation modeling
Preferred skills
CPU microarchitecture knowledge, RTL design understanding, CAD tool expertise, timing methodology definition, large SoC signoff experience, transistor fundamentals, worst-case corner selection
Technologies
Verilog, CAD tools, standard cell libraries, FPGA/DSP systems (contextual)
Responsibilities
Define, implement, and validate timing constraints with microarchitecture and RTL teams; Perform STA at block, cluster, and SoC levels across multiple modes and corners; Analyze timing on frequency-critical paths and drive logic/micro-architectural fixes; Provide actionable timing feedback to physical design engineers; Partner with CAD teams to develop CPU-specific timing flows; Generate and review timing ECOs to close violations; Contribute to timing methodology definition and documentation.
Seniority
Staff/Sr Staff, hands-on IC
