Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
Core
Design and deploy next-generation high-speed HBM/LPDDR/DDR memory subsystems, including controllers and NoCs, interfacing with CPU, GPU, DSP, and multimedia processors.
Role type
Senior ASIC Digital Design Engineer (Memory Subsystem)
Builds
High-speed memory controllers and cache architectures for Qualcomm mobile and computing products
Domain
Semiconductors / High-Speed Digital Design
Required skills
RTL coding, ASIC front-end digital design, Hardware Architecture, Synthesis, Timing Closure, Physical Design Support, Gate Level Simulation, Power Analysis, Memory transaction ordering
Preferred skills
HBM memory design, On-chip SRAM & L3 cache controller architecture, x86 or ARM CPU/bus architectures, RTL Design Verification flows
Technologies
HBM, LPDDR, DDR, NoC, SRAM, L3 cache, x86, ARM
Responsibilities
Develop architecture and design specifications for memory subsystems, implement RTL code, debug designs and provide support during integration, contribute to design methodology improvements
Seniority
Senior, hands-on IC
